Stage 1 (gains)
research_required
Stage 1 (prix indicatif)
research_required
Temps d'intervention
research_required
Outils nécessaires
research_required
Architecture
Tricore/SPC Power Architecture class
微控制器 (MCU)
TC1762 / TC1766
Mémoire / Flash
1.5MB internal flash
Lecture / écriture possible
Variable selon méthode utilisée
Protocole de communication
Boot/Bench tool application list
Cadre légal
FR/DE/CH/EU: road use may be illegal if emissions/noise/type-approval affected; track/export disclaimer required; verify local law